1. Field of the Invention
The present invention relates to image recording technology for recording an image on a record medium such as paper, film, etc., and more specifically to the technology for controlling a recording position according to the conveyance information during conveyance of the record medium on which the image is recorded.
2. Description of the Related Art
For example, a full-line color ink jet system is well known as an image recording apparatus. In the image recording apparatus, a plurality of nozzle arrays for jetting ink are arranged in a direction orthogonal to the conveyance direction (secondary scanning direction) in which a record medium is conveyed and at predetermined intervals in a secondary scanning direction by ink color. With this image recording apparatus, a character and an image are recorded on a record medium arranged opposite the plurality of nozzle arrays by jetting ink of each color from a plurality of nozzle arrays.
Relating to the above-mentioned technology, for example, Japanese Laid-open Patent Publication No. 2007-253337 discloses the nozzle array driving method using a phase locked loop (PLL) for inputting an encoder signal as the technology of controlling the nozzle array of an image recording apparatus. With this technology, a control signal corresponding to the timing of jetting ink is generated by performing control by a phase locked loop corresponding to the conveying speed of the record medium according to the encoder output signal generated corresponding to the amount of conveyance of the record medium.
With the technology, a signal obtained by multiplying the frequency of the output signal of the encoder provided for the conveyance path of the record medium by n (n is a natural number) is generated using the phase locked loop, and an ink jet timing control signal corresponding to each nozzle array is generated using the generated signal. When the value of n is changed, the frequency of the ink jet timing control signal changes with respect to the record medium conveyed at a predetermined speed. Therefore, with the technology, the resolution in the secondary scanning direction in recording an image can be changed.
In addition, with the technology disclosed by the above-mentioned document, the streaky unevenness (appearing in a recorded image) can be suppressed by setting the value of the set value n corresponding to each speed to perform a recording operation at ½ to quadruple speeds with respect to the conveying speed of the record medium.
Described below is the configuration illustrated in FIG. 1. FIG. 1 illustrates the common configuration of a phase locked loop disclosed by the above-mentioned document.
A phase locked loop 41 is configured by a phase comparator 42, a loop filter 43, a voltage control oscillator 44, and a frequency divider 45.
The phase comparator 42 detects a phase shift between the pulse signal of an encoder as a pulse interval corresponding to the conveying speed of a record medium (conveyance distance per unit time) and a feedback signal 45a obtained by feeding back a clock signal 44a as the output of the phase locked loop 41 through the frequency divider 45. A signal 42a indicating the phase shift can be converted into a loop filter output 43a as a signal of a voltage value corresponding to the level of the advance/delay of the phase by passing through the loop filter 43.
The voltage control oscillator 44 outputs the clock signal 44a of the frequency corresponding to the voltage value of the loop filter output 43a. The frequency divider 45 outputs the feedback signal 45a obtained by frequency-dividing the clock signal 44a output from the voltage control oscillator 44 to the phase comparator 42.
The ink jet timing is determined by the clock signal 44a output of the voltage control oscillator 44. The clock signal 44a is a signal synchronous to the conveying speed of a record medium and, according to the dividing ratio set value n of the frequency divider 45, the clock signal 44a is obtained as a signal of an n-time frequency of the pulse signal generated by the encoder.
Described below is the configuration illustrated in FIG. 2. FIG. 2 illustrates an ideal ink jet timing control signal (of the same frequency as the clock signal 44a illustrated in FIG. 1) when the conveying speed of a record medium is predetermined. Thus, it is desired that the ink jet timing control signal has a stable period T. In this example, the rising edge of the ink jet timing control signal is used for the drive timing of a nozzle array.
Described below is the example illustrated in FIG. 3. FIG. 3 illustrates an example of the V-F characteristic (voltage to frequency characteristic) of the voltage control oscillator 44.
The frequencies of the clock signal 44a output from the voltage control oscillator 44 are higher and lower than the target frequency Ft by the voltage of the loop filter output 43a as illustrated in FIG. 3. If the frequency of the clock signal 44a is thus shifted from the target frequency Ft, there occurs an error in the ink jet timing. The fluctuation of the period corresponding to the shift of the frequency is generally referred to as a jitter.
The range from fL to fH illustrated in FIG. 3 refers to the range of the frequency at which the voltage control oscillator 44 can output a signal of a stable frequency with respect to the voltage change range of the loop filter output 43a, and it is generally referred to as a lock range of the phase locked loop 41. FIG. 3 illustrates a signal of the frequency fL output when the lowest voltage VL of the loop filter output 43a is input to the voltage control oscillator 44, and a signal of the frequency fH output when the highest voltage VH of the loop filter output 43a is input to the voltage control oscillator 44.
Described next is the concept illustrated in FIG. 4. FIG. 4 illustrates the concept of the correlation among the signal waveforms of the units of the phase locked loop 41 illustrated in FIG. 1.
In FIG. 4, part (a) indicates by broken lines the waveform of a pulse signal input to the phase locked loop 41, and illustrates by solid lines the waveform of the feedback signal 45a. Part (b) indicates the waveform of the signal 42a of the phase comparator 42 at this time. Part (c) indicates the waveform of the loop filter output 43a at this time.
In FIG. 4, the waveform of part (a) indicates the phase delay of the rising edge of the feedback signal 45a by ΔT (ΔT0, ΔT1, ΔT2, . . . ) with respect to the encoder signal. Since the value of ΔT (ΔT0, ΔT1, ΔT2, . . . ) is different, the feedback signal 45a includes a jitter component.
The phase comparator 42 outputs a pulse signal of a pulse width ΔT (ΔT0, ΔT1, ΔT2, . . . ) corresponding to the phase delay as the output signal 42a as indicated by part (b). The loop filter 43 outputs as the loop filter output 43a the voltage fluctuating up and down from the reference voltage by the ΔA (ΔV0, ΔV1, ΔV2, . . . ) corresponding to the pulse signal as the output signal 42a as indicated by part (c). The V0 in part (c) indicates the voltage fluctuation range of the loop filter output 43a generated by the jitter component included in the feedback signal 45a indicated by part (a).
FIG. 3 further illustrates the frequency fluctuation Δf (Δf0, Δf1, Δf2, . . . ) of the output signal (that is, the clock signal 44a) of the voltage control oscillator 44 generated by the voltage fluctuation ΔV (ΔV0, ΔV1, ΔV2, . . . ) of the loop filter output 43a. Fα illustrated in FIG. 3 indicates the frequency fluctuation range of the output signal (that is, the clock signal 44a) of the voltage control oscillator 44 when the voltage fluctuation range of the loop filter output 43a is V0. That is, the jitter component included in the feedback signal 45a indicated by part (a) illustrated in FIG. 4 generates the frequency fluctuation over the range of Fα on the clock signal 44a. 
In FIG. 3, the relationship between the voltage fluctuation range V0 of the loop filter output 43a and the frequency fluctuation range Fα of the output signal (that is the clock signal 44a) of the voltage control oscillator 44 is determined by the tilt of the straight line indicating the V-F characteristic of the voltage control oscillator 44. When the voltage range (from VL to VH in FIG. 3) of the loop filter output 43a is fixed, and if the lock range (from fL to fH in FIG. 3) of the voltage control oscillator 44 is wide, the tilt of the straight line indicating the V-F characteristic is high. At this time, the frequency fluctuation range Fα of the output signal (that is, the clock signal 44a) of the voltage control oscillator 44 with respect to the voltage fluctuation range V0 of the loop filter output 43a becomes wide. The fluctuation of the frequency is generated by the jitter component of the feedback signal 45a. 
Thus, the jitter component of the clock signal 44a increases when the lock range of the voltage control oscillator 44 becomes wider, which expands the shift of the recording position on the record medium.
However, in the technology disclosed by the Japanese Laid-open Patent Publication No. 2007-253337, the lock range of the phase locked loop 41 illustrated in FIG. 1 is set wide to correspond to the change of the conveying speed of the record medium of ½ through quadruple conveying speed.